Part Number Hot Search : 
PC901 20N120 TDA2006 STB607F A8980CJT 88ASR 10125 9425G
Product Description
Full Text Search
 

To Download MC74F195 Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 MC74F195 4-BIT PARALLEL ACCESS SHIFT REGISTER
The functional characteristics of the MC74F195 4-Bit Parallel Access Shift Register are indicated in the Logic Diagram and Function Table. The device is useful in a wide variety of shifting, counting, and storage applications. It performs serial, parallel, serial-to-parallel, or parallel-to-serial data transfers at very high speeds. The MC74F195 operates in two primary modes, shift right (Q0-Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is HIGH, and is shifted 1 bit in the direction Q0-Q1-Q2-Q3 following each LOW-to-HIGH clock transition. The J and K inputs provide the flexibility of the JK type input is made for special applications, and by tying the two pins together the simple D-type input is made for general applications. The device appears as four common clocked D flip-flops when the PE input is LOW. After the LOW-to-HIGH clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input LOW. All parallel and serial data transfers are synchronous, occurring after each LOW-to-HIGH clock transition. The MC74F195 utilizes edge-triggering; therefore, there is no restriction on the activity of the J, K, Dn, and PE inputs for logic operation, other than the setup and hold time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition. * Shift Right and Parallel Load Capability * J-K (D-Type) Inputs to First Stage * Complement Output from Last Stage * Asynchronous Master Reset
4-BIT PARALLEL ACCESS SHIFT REGISTER
FASTTM SCHOTTKY TTL
J SUFFIX CERAMIC CASE 620-09
16 1
16 1
N SUFFIX PLASTIC CASE 648-08
16 1
D SUFFIX SOIC CASE 751B-03
ORDERING INFORMATION CONNECTION DIAGRAM DIP
VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 Q3 11 CP 10 PE 9 MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC
LOGIC SYMBOL
9 2 1 MR 2 J 3 K 4 D0 5 D1 6 D2 7 D3 8 GND 10 3 J 45 6 7
PE D0 D1 D2 D3 11
Q3 CP K MR Q0 Q1 Q2 Q3 1 15 14 13 12 VCC = PIN 16 GND = PIN 8
FAST AND LS TTL DATA 4-104
MC74F195
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 -1.0 20 Unit V C mA mA
LOGIC DIAGRAM
J PE K D0 D1 D2 D3
CP MR R RD Q R RD R RD R RD Q
CP S Q Q0
CP S Q Q1
CP S Q Q2
CP S Q Q3 Q3
FUNCTION TABLE
Inputs Operating Modes Asynchronous Reset Shift, Set First Stage Shift, Reset First Stage Shift, Toggle First Stage Shift, Retain First Stage Parallel Load MR L H H H H H CP X PE X h h h h l J X h l h l X K X h l l h X Dn X X X X X dn Q0 L H L q0 q0 d0 Q1 L q0 q0 q0 q0 d1 Outputs Q2 L q1 q1 q1 q1 d2 Q3 L q2 q2 q2 q2 d3 Q3 H q2 q2 q2 q2 d3
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care dn (qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition. = LOW-to-HIGH clock transition
FAST AND LS TTL DATA 4-105
MC74F195
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.5 2.7 0.5 20 100 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current -60 -0.6 -150 38 mA mA mA Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A IOL = 20 mA VIN = 2.7 V VIN = 7.0 V VCC = MAX VOUT = 0 V VCC = MAX VCC = MAX Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = -18 mA IOH = -1.0 mA VCC = MIN VCC = 4.5 V VCC = 4.75 V VCC = 4.5 V VCC = MAX
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
54/74F TA = + 25C VCC = + 5.0 V CL = 50 pF Symbol fmax tPLH tPHL tPHL tPLH Propagation Delay CP to Q/Q Propagation Delay, MR to Q Propagation Delay, MR to Q Parameter Min 105 2.5 2.5 3.0 3.0 7.0 8.0 10 10.5 Max Min 90 2.5 2.5 3.0 3.0 8.0 9.0 11 11 ns ns 74F TA = 0C to + 70C VCC = 5.0 V 10% CL = 50 pF Max Unit MHz ns
FAST AND LS TTL DATA 4-106
MC74F195
AC OPERATING REQUIREMENTS
74F TA = + 25C VCC = + 5.0 V CL = 50 pF Symbol ts (H) ts (L) th (H) th (L) ts (H) ts (L) th (H) th (L) tw (H) tw (L) trec CP Pulse Width, HIGH MR Pulse Width, LOW Recovery Time, MR to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW J, K, D to CP Parameter Setup Time, HIGH or LOW J, K, D to CP Min 4.0 4.0 0 0 8.0 8.0 0 0 5.0 5.0 7.0 Max Min 4.0 4.0 1.0 1.0 9.0 9.0 0 0 5.5 5.0 8.0 ns ns ns ns ns ns 74F TA = 0C to + 70C VCC = 5.0 V 10% CL = 50 pF Max Unit ns
FAST AND LS TTL DATA 4-107


▲Up To Search▲   

 
Price & Availability of MC74F195

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X